Verilink SCC 2020 (880-503268-001) Product Manual Manual de usuario descargar pdf (Pagina 49)

Configuration

Verilink SCC 2020 User Manual

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58 SCC 2020

TAC 2010

DIU 2140

Set data bus to C (Mux mode)

59 SCC 2020

TAC 2010

TAC 2130

Send in-band CSU loop-up code to far-end CSU, this should cause the

far end CSU to enter a Line Loopback condition

60 SCC 2020

TAC 2010

TAC 2130

Send framed QRSS to far end

61 SCC 2020

TAC 2010

TAC 2130

Stop QRSS pattern and send inband CSU loop-down code to far end

62 DIU 2140 Use timeslot 24 on the assigned CSU, set all 5 data ports to 9.6 kbit/s

63 DIU 2140 Selects split timing (RX clock ~ TX clock); typical value

64 DIU 2140 Selects single source timing (RX clock = TX clock);

65 DIU 2140 Sets DTE timing option for all synchronous data ports to ST

66 DIU 2140 Sets DTE timing option for all synchronous data ports to ST

67 DIU 2140 Sets DTE timing option for all synchronous data ports to TT

68 DIU 2140 Sets RTS to normal operation, for synchronous data ports, data is

transmitted ONLY if the DTE asserts RTS, (ignored in Async) [default]

69 DIU 2140 Sets RTS to forced on (requires version 1.1 DIU 2140 firmware), data is

sent regardless of actual state of RTS from DTE: this behavior always

applies to Async ports

80 DIU 2130

TAC 2130

Set Data Port 1 to tail-circuit timing. Note that TAC 2130-T and TAC

2130-S modules do not support tail circuit timing, external timing or

TIU 2850 timing

81 TAC 2130

DIU 2130

Canned configuration #1, assigns all 24 timeslots to data port #1

82 TAC 2130

DIU 2130

Canned configuration #2, assigns timeslots 1-12 to data port #1 and

timeslots 13-24 to data port #2 (data port #2 ignored by TAC 2130)

83 TAC 2130

DIU 2130

Canned configuration #3, assigns timeslots 1-8 to data port #1 and

timeslots 9-16 to data port #2 (data port #2 ignored by TAC 2130)

84 TAC 2130

DIU 2130

Canned configuration #4, assigns timeslots 1-6 to data port #1 and

timeslots 7-12 to data port #2 (data port #2 ignored by TAC 2130)

85 TAC 2130

DIU 2130

Canned configuration #5assigns timeslots 1-4 to data port #1 and

timeslots 5-8 to data port #2 (data port #2 ignored by TAC 2130)

86 TAC 2130

DIU 2130

Canned configuration #6, assigns timeslots 1-2 to data port #1 and

timeslots 3-4 to data port #2 (data port #2 ignored by TAC 2130)

Code Applies to Description

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Verilink SCC 2020 (880-503268-001) Product Manual Manual de usuario Pagina 49

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